1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device, such as a dynamic random access memory (DRAM), which includes a test circuit for detecting leakage failure in memory cell transistors.
2. Description of the Background Art
As a test method (hereinafter, referred to as “a disturb refresh test”) for detecting leakage failure in memory cell transistors in a conventional semiconductor memory device, or in particular, in DRAM, there is, for example, the following method.
First, high (or low) data is written into all memory cells (write operation). After writing the data into all the memory cells, any word lines are activated and charges in the memory cells are read out to bit lines intersecting the activated word lines. And by amplifying the read-out charges in a sense amplifier circuit (read/refresh operation), potentials in the bit lines and complementary bit lines are made high or low. This state is maintained for a guaranteed period of data retention time (hereinafter, referred to as “refresh test time) for memory cells.
In this state, in memory cell capacitors connected to unselected word lines, high data is held, and in memory cells connected to bit lines whose levels are low, potential differences arise between sources and drains of memory cell transistors, and subthreshold currents flow. Here, in a case of memory cells whose transistor threshold voltages are low, since large subthreshold currents flow, data cannot be held within refresh test time and the memory cells become defective. Therefore, after the end of the refresh test time, a readout operation is carried out for memory cells which are targeted for test and it is confirmed whether data can be correctly read out.
However, the potentials in the bit lines and the complementary bit lines in memory cells connected to the unselected word lines can be made high or low only on a memory cell array to memory cell array basis, with the memory cell array including a memory cell group and a sense amplifier circuit. The above-mentioned refresh test time is often set in several ms to several tens ms and is sufficiently long as compared with time required for reading out and writing data in the memory cells. Therefore, the disturb refresh test time occupies a large proportion of memory test time. As a process which allows further miniaturization and speeding-up is increasingly being developed, a memory cell array has been downscaled, resulting in an increase in the number of memory cell arrays.
In order to solve these problems, a method in which a plurality of word lines are concurrently activated in accordance with a test mode and a method in which a reduction in the above-mentioned disturb refresh test time is devised by concurrently selecting a plurality of memory cell arrays have been employed. For example, refer to Japanese Patent No. 3238806 (pages 3 to 5, FIG. 1).
However, in the above-mentioned conventional methods, in order to realize the concurrent activation of the plurality of word lines and the concurrent selection of the plurality of memory cell arrays, interposing a test mode signal in a logic gate of an address decoding circuit is required. Therefore, the conventional methods not only increase an area of a control circuitry section but also delay a row decoding signal, leading to a problem of impeding a high-speed operation of a memory.